Reproducibility Archive for "The E80 Microworld: A Gate-Transparent CPU and One-Click Toolchain in Structural VHDL"

This archive provides the standardized protocol and raw data for reproducing the place-and-route phase of the E80 soft-core design. It includes the analytical data for Maximum Frequency, Critical Path, and Resource Usage across three distinct FPGA toolchains (OSS CAD Suite, Gowin, and Quartus). The archive contains data for two major design iterations: Version 2.0 (raw VHDL source files prior to combinational loop optimization) and Version 4.0 (the final packaged toolchain).