Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]

Name: Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]
Creator: Zenodo
Published: 2021-11-22T18:48:57+08:00

Zenodo2021-11-22 更新2026-05-25 收录

数据链接：

https://zenodo.org/record/5595286 数据链接链接失效反馈

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资源简介：

Source code of paper "Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference" submitted to FPGA'22 for artefact evaluation.

提供机构：

Zenodo

创建时间：

2021-11-22

Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]

资源简介：

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