Name: Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]
Creator: Zenodo
Published: 2021-11-22 18:48:58
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Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [Artefact Evaluation]

Source code of paper "Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference" submitted to FPGA'22 for artefact evaluation.

Zenodo2021-11-22 更新00

FPT 2025 "Efficient FPGA Resource Graph Learning with Graph Neural Networks for Router Runtime Prediction" Data

Data for the 2025 International Conference on Field Programmable Technology (FPT 2025) paper "Efficient FPGA Resource Graph Learning with Graph Neural Networks for Router Runtime Prediction" by Gunter

Zenodo2025-11-18 更新00

Convolutional Neural Networks for Valid and Efficient Causal Inference

Convolutional neural networks (CNN) have been successful in machine learning applications. Their success relies on their ability to consider space invariant local features. We consider the use of CNN

NIAID Data Ecosystem00