芯片可靠性研究与FUXI-EC芯片研制数据集

芯片研制过程主要面向芯片设计验证、可靠性设计评估和功耗控制技术，针对满足电力工业应用环境和可靠稳定工作需求，进行多核异构芯片的容错能力和能效的优化研究，构建故障注入平台、电力芯片能耗模型、多核芯片低功耗验证系统、芯片能耗调节方法等。电力芯片研制数据集是基于多核处理器片上系统基础上，记录了多处理器系统任务容错调度、不同功耗链路特征的能量值，以及多核处理器调度模块、多核异构芯片能耗优化模块等仿真数据。

The chip development process mainly focuses on chip design verification, reliability design evaluation, and power consumption control technologies. To meet the operational requirements of power industry application scenarios and the demand for reliable and stable working conditions, it conducts optimization research on the fault tolerance capability and energy efficiency of multi-core heterogeneous chips, and constructs relevant facilities including fault injection platforms, power chip energy consumption models, low-power verification systems for multi-core chips, and chip energy consumption adjustment methods.

The power chip development dataset is built on the basis of multi-core processor system-on-chips (SoCs), and records the energy values of task fault-tolerant scheduling in multi-processor systems and energy values corresponding to different power consumption link characteristics, as well as simulation data from modules such as multi-core processor scheduling modules and energy efficiency optimization modules for multi-core heterogeneous chips.

搜集汇总

背景与挑战

背景概述

该数据集聚焦于芯片可靠性研究与FUXI-EC芯片研制，主要面向电力工业应用环境，涵盖芯片设计验证、可靠性评估和功耗控制技术。数据集包含多核异构芯片的容错调度、能耗优化等仿真数据，涉及故障注入平台和能耗模型构建，旨在支持多核处理器系统的能效和稳定工作优化。数据来源于浙江大学的国家重点研发计划项目，以仿真数据为主，适用于集成电路和半导体技术领域的研究。