Gate-Level RTL Description of the Glitch Optimized Multipliers

This paper presents a novel implementation schemeof the essential circuit blocks for high performance, full-precisionBooth multipliers leveraging a hybrid logic style. By exploitingthe behavior of parasitic capacitance of MOSFETs, a carefullyengineered design style is employed to reduce dynamic power dissipationwhile improving the glitch immunity of the circuit blocks.The circuit-level techniques along with the proposed signal-flowoptimization scheme prevent the generation and propagationof spurious activities in both partial-product and adder-treestages. Two full-precision Booth multipliers built from proposedstrategies were compared to the state-of-the-art versions knownfrom literature by means of extensive post-layout simulationsin 65-nm CMOS technology. The proposed versions on averagedemonstrated up to 10% and 30% power savings in general.