Latchup characterization of 7-nm technology node using neutron beam at ChipIR

Semiconductor industry is currently offering 7 nm technology node with FinFET fabrication processes. Latchup causing mechanisms and rates for FinFET technologies are expected to be vastly different from those for planar technologies. This proposal is for the investigation of neutron-induced latchup for 7 nm circuit designs. We will be using test ICs containing sequential circuit designs . Since latchup may actually destroy the IC functionality, tests are needed to estimate neutron-induced failure rates to allow for development of predictive models. Results from these experiments will be supported with TCAD simulations and circuit simulations. Results will support a dissertation and will be disseminated through publications at conferences and journals