VNWFET-Based Standard Cell Library

Vertical Nanowire Field Effect Transistors (VNWFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization thus enabling logic synthesis. From here, and using a compact model of laboratory-scale VNWFET technology, we started by the characterization of basic logic cells and with different drive strength ( i.e. different number of nanowires) ending up with a VNWFET based standard cell library. The current version of the logic cell library is generated by Liberate™ (Cadence®). The library is named JLNT and is composed of the following logic cells:

4 instances of INV1_1_Static_JL1 corresponding to 4,24,44 and 64 NW named as Xinvx1
3 instances of NAND2_1_Static_JL1 corresponding to 4,24 and 44 NW named as Ynand2x1
3 instances of NOR2_1_Static_JL1corresponding to 4,24 and 44 NW named as Ynor2x1
3 instances of XOR2_1_Static_JL1 corresponding to 4,24 and 44 NW named as Yxor2x1
DFFSR (synchronous reset)
where X ∈ {1, 2, 3, 4}, Y ∈ {1, 2, 3} and the formalism OPnXk_Style_Technology indicates the Boolean operation OP, the number of inputs n and the number of outputs k, as well as the logic design style and the technology variant used to implement the cells.
This work has been founded by FVLLMONTI European Union's Horizon 2020 research.