Integrated ML and XAI Pipeline for Transistor Quantification in CMOS JK Flip-Flop Designs

Name: Integrated ML and XAI Pipeline for Transistor Quantification in CMOS JK Flip-Flop Designs
Creator: Zenodo
Published: 2026-01-13T04:45:51+08:00

Zenodo2026-01-19 更新2026-05-26 收录

数据链接：

https://zenodo.org/doi/10.5281/zenodo.18228017 数据链接链接失效反馈

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资源简介：

Customized database, created from the Cadence CMOS simulation setup, which is utilizedfor training the ML model.

提供机构：

Zenodo

创建时间：

2026-01-13

Integrated ML and XAI Pipeline for Transistor Quantification in CMOS JK Flip-Flop Designs

资源简介：

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