PROJECT VORTEX-ION: In-Situ Pyro-Catalytic Filter Loop (Model VXI-4000)

📄 Zenodo Repository Description Title An Asymmetric Multiprocessing (AMP) Framework and Hardware Isolation Protocol for Co-Located In-Situ Real-Time Safety Core Monitoring on Dual-Core Silicon Abstract / Technical Summary This repository contains the complete, production-certified bare-metal source tree, absolute linker maps, memory safety drivers, and hardware deployment scripts for Project Vortex-Ion. This architecture implements a highly deterministic, co-located in-situ safety core monitoring framework running on the STMicroelectronics STM32H747 dual-core ARM Cortex-M7/M4 microcontroller. The primary objective of this subsystem is the real-time, zero-latency parsing of critical in-situ industrial process telemetry (including pyrometer thermal arrays, nitrogen curtain purge pressures, and differential filter profiles) inside high-hazard environments. To achieve absolute reliability, the architecture enforces a strict Asymmetric Multiprocessing (AMP) sandboxing layout. The Cortex-M4 secure safety core is entirely air-gapped into isolated RAM (SRAM4), operating with zero dependencies on primary Flash or System SRAM, completely decoupling it from the non-deterministic, high-overhead material and economic projection models executing concurrently on the 480 MHz Cortex-M7 master core. Key Microarchitectural & Isolation Features In-Situ Telemetry Cache Alignment: The shared in-situ telemetry data structure (VXI_InSitu_Telemetry_t) is meticulously serialized, packed, and balanced to measure exactly 32 bytes (the precise length of an ARM L1 data cache line). This geometry completely eliminates multi-core cache-line thrashing and allows the Cortex-M7 application core to perform unified, single-instruction cache maintenance (dc ivac / dc cvac) directly to the Point of Unification (PoU) at the physical SRAM4 boundary. C11 Hardware-Fence Atomics: Multi-core race conditions and shared bit-erasure are neutralized via strict C11 hardware atomic intrinsics (__atomic_or_fetch / __atomic_fetch_add). This forces the compiler to generate true LDREX and STREX assembly structures arbitrated by the system interconnect's Global Exclusive Monitor, protecting the volatile shared telemetry memory domain during simultaneous multi-core read-modify-write operations. Optimized 3-Slot MPU Isolation Driver: The Cortex-M4 secure core enforces rigid hardware perimeters via an optimized Memory Protection Unit (MPU) layout using empty inline assembly fences (__asm volatile("" ::: "memory")) to guarantee strict register serialization under -O3 compilation passes. It consolidates the contiguous 48KB executable code space into a single hardware slot (Region 0) via a Sub-Region Disabling (SRD) mask (0xC0), completely freeing up MPU slot assets. Region 1 locks the variable data and stack workspace to Execute-Never (XN) and Normal Non-Cacheable modes, while Region 2 maps a uniform 512MB Device Memory region (TEX=010) to provide safe access to APB/AHB peripherals across the D1, D2, and D3 silicon domains without crossbar switch matrix stalls. Zero-RAM-Write Escape Path & Fail-Safe Mechanics: The early assembly startup layers utilize compiler-driven section geometry padding (. = ALIGN(4)) to execute maximum-burst memory clearing loops that land precisely on section margins. Dynamic stack-overflow verification loops check the live stack register (sp) against an absolute global anchor constant. Upon boundary breach detection, the core bypasses all volatile memory modifications and deploys an atomic hardware store to the Bit Set/Reset Register (VXI_GPIOG_BSRR) to instantly latch emergency bypass pneumatics and gravity blast gates, freezing the CPU via a low-power while(1) { __WFI(); } loop to gracefully isolate a compromised core. Parallel-Safe Build Engine & Synchronized Deployment: The unified Makefile provides an explicit dependency graph supporting multi-threaded concurrent compilation (make -j) while tightly mirroring optimization flags (-O3 -flto) across compilation and final link passes to ensure absolute symbol preservation. Post-build auditing targets invoke readelf to mathematically verify security boundaries at compile time. OpenOCD and GDB scripting profiles automate dual-port SWD Coresight DAP connections to flash, verify, and debug both targets independently over ports 3333 and 3334. Repository File Manifest vxi_sys_flash.cfg: Master OpenOCD deployment and SWD target flashing automation script. vxi_gdb_sync.gdb: Multi-core target context synchronized breakpoint and debugging profile (unhidden for Zenodo indexing). deploy.txt: Formal deployment manual, microarchitectural mapping guidelines, and operational README. Makefile: Hardware diagnostics and parallel-safe AMP cross-compilation build engine. core_m4_safety/: Core folder containing the Cortex-M4 secure safety runtime, including: src/safety_core_m4.c: Clean-store Write-1-to-Clear (W1C) interrupt routines and type-safe strict-aliasing sensor checking loops. src/mpu_config_m4.c: Multi-domain peripheral whitelisting and 3-slot hardware-level sandboxing engine. linker_sram4.ld: Absolute memory layout map preventing binary zero-padding explosions. startup_stm32h747_m4.s: Ultra-low latency assembly vector loader and burst-efficient data copy loops. inc/vortex_ion_insitu.h: Strict lvalue-dereferenced constant register maps and the 32-byte cache-line balanced telemetry array block. core_m7_app/: Core folder containing the Cortex-M7 master application core code, including: src/main_m7.c: Real-time yield monitoring loops and master clock tree release sequence. linker_flash.ld: Deep 16KB stack application layer flash configuration script. startup_stm32h747_m7.s: High-performance master application core boot vector assembly layout.