Performance analysis of the Junction-less Gate All Around (JL-GAA) MOSFET and Charge Plasma Technique based Junction-less Gate All Around (CPT-JL-GAA) MOSFET on Experimental Data

This paper covers the Performance analysis of the Junctionless Gate All Around (JL-GAA) MOSFET and Charge Plasma Technique based Junctionless Gate All Around (CPT-JL-GAA) MOSFET on Experimental Data. For high-speed ULSI chip design, both are promising solutions. There is no physical junction in both the devices at source to channel and channel to drain Interface. There is no doping concentration gradient for specific regions; therefore, device fabrication becomes easier than the planer MOSFETs. Experimental data for the analog performance of both the devices have been extensively extracted from ATLAS-3D Device Simulator. Analog performance date parameters are also compared. It is found that the Charge Plasma Technique based Junction less Gate All Around (CPT-JL-GAA) MOSFET are better for analog performance in comparison to Junction less Gate All Around (JL-GAA) MOSFET.

本文深入探讨了基于实验数据的Junctionless Gate All Around (JL-GAA) 沟道环绕型金属氧化物半导体场效应晶体管（MOSFET）以及基于电荷等离子体技术（Charge Plasma Technique, CPT）的Junctionless Gate All Around (CPT-JL-GAA) MOSFET的性能分析。对于高速超大规模集成电路（ULSI）芯片设计，这两种技术均展现出巨大的潜力。在源极至沟道以及沟道至漏极的界面处，这两种器件均未形成物理结点；此外，特定区域不存在掺杂浓度梯度，因此相较于平面型MOSFET，其器件制造过程更为简便。通过对ATLAS-3D器件模拟器进行广泛的数据提取，得出了两种器件的模拟性能数据。同时，对模拟性能数据参数进行了比较。研究发现，相较于Junctionless Gate All Around (JL-GAA) MOSFET，基于电荷等离子体技术的Junctionless Gate All Around (CPT-JL-GAA) MOSFET在模拟性能方面更为优越。