Side-channel analysis on masked-AES implementation on ARM M3

A data set of power traces that was acquired from executing a two-shares masked AES SubBytes implementation (written in Thumb Assembly Language) on an ARM Cortex M3 processor core from NXP (LPC1313). This implies that no single point leaks information about the unshared intermediate value, further confirmed via leakage detection. We use a custom measurement board (Picoscope 5243D), which provides good measurements (at 250 MSa/s, and the working frequency is set to 2 MHz). We use our scope in a basic setting to avoid any trace processing (de-noising) and extract discrete traces (5 million), where each point is represented by 8 bits. We have uploaded a compressed version of .trs file. We have used the data for our paper "Leakage Certification Made Simple"