VeriSFQ

VeriSFQ是一个针对单磁通量子（SFQ）电路的半形式验证框架和基准，由南加州大学电气与计算机工程系开发。该数据集包含11个组合SFQ电路，用于展示SFQ逻辑特性，如扇出、门级流水线、路径平衡和输入到输出延迟。数据集的创建过程中，使用了SFQ逻辑综合工具SFQmap来生成等效的门级结构模型，并通过预处理确保电路的扇出和路径平衡。VeriSFQ框架主要应用于验证SFQ电路的关键电路和门级属性，旨在解决SFQ电路验证技术相对于CMOS逻辑的不足问题。

VeriSFQ is a semi-formal verification framework and benchmark for Single Flux Quantum (SFQ) circuits, developed by the Department of Electrical and Computer Engineering, University of Southern California. This dataset includes 11 combinational SFQ circuits designed to showcase SFQ logic characteristics such as fanout, gate-level pipelining, path balancing, and input-to-output delay. During the dataset's creation, the SFQ logic synthesis tool SFQmap was used to generate equivalent gate-level structural models, and preprocessing was implemented to ensure proper fanout and path balancing of the circuits. The VeriSFQ framework is primarily applied to verify key circuit-level and gate-level properties of SFQ circuits, with the objective of addressing the limitations of SFQ circuit verification technologies relative to those for CMOS logic.