Error tolerant multimedia compression system

Unrestricted All existing digital system design approaches strive to provide error-free values at system outputs, which is achieved by using testing techniques, as well as defect and fault tolerant methods. In contrast, the focus of this thesis is on error tolerant systems, i.e., systems where certain types of errors at system outputs can be tolerated, provided their severities are below certain levels. The overall objective of our research in error tolerance is (i) to identify the inherent ability of some systems to tolerate errors, and (ii) to develop design and test approaches that exploit this ability.; Our target systems are multimedia applications, which represent a major workload on major hand-held devices such as cellular phones and laptops. Video coders (e.g., H.264/AVC and MPEG-4) and image coders (e.g., JPEG and JPEG2000) are the most complex part of multimedia applications. Within a typical video/image coder, we focus on motion estimation (ME) and linear transforms (e.g., discrete cosine transform) as those two consume a large percentage of resources. Achieving error tolerance in those two modules can lead to increased yield or lower power consumption.; In this thesis, we study two specific scenarios i) soft-error tolerance in matching metric computations within motion estimation, ii) hard-error tolerance in linear transforms (e.g., discrete cosine transform). While soft errors can also be introduced due to deep submicron (DSM) noise, we focus on voltage over scaling which introduces input-dependent errors. We show that soft errors within matching metric computation of motion estimation are tolerable to some extent. The tolerance to soft errors of the motion estimation module is exploited in a low power motion estimation system; i.e., the motion estimation module can operate (with someerror) at a lower voltage configuration, thus achieving power savings. We first explore one possible configuration which uses one voltage over scaled metric computation within ME. We then extend that work to a more general configuration using multiple low complexity metric computations (e.g., voltage over scaled and sub-sampled metrics) within ME.; Hard errors are introduced due to defects within hardware. By emulating the effect of those hard errors within linear transform hardware, we show that linear transforms have significant error tolerance. This error tolerance is exploited in order to achieve a higher yield rate by accepting systems with faults, while still operate with acceptable quality. To realize this, we introduce a systematic error tolerant testing method for this hardware.