Data for: Investigation of the Stepped Split Protection Gate L-Trench SOI LDMOS with Ultra-Low Specific On-Resistance by Simulation

Fig.3. Output capacitance versus effective gate voltage, VG-VT. Fig. 4. Comparison of transfer characteristics among the three structure at Vds = 25 V. Fig. 5. Thermal characteristics curves of (a) Con. LDMOS, TG LT LDMOS, and SSG LT LDMOS surface temperature characteristics along the drift region. (b) Temperature as a function of Tox thickness variation. Fig. 6. The relationship between drain voltage and current at breakdown. equi-potential contours of three devices, the proposed device, BV = 117 V, Con. LDMOS, BV = 101 V and TG LT LDMOS, BV = 102 V is shown as an insert. Fig. 7. The dependence of the Nd as a function of the BV and Ron,sp. Fig. 8. shows the influence of the Wt on the BV and FOM of the SSG LT LDMOS. The inset shows the effect of the left trench width on the BV of the device. Fig. 9. The effect of the thickness variation of the buried oxide layer on the BV of the device at the breakdown (a) The effect of Tox thickness variation on BV (Wt=0.5µm). (b) The charge concentration on both sides of the buried oxide layer corresponding to different buried layer thicknesses. Fig. 10. BV, Ron,sp and FOM of SSG LT LDMOS versus PG oxide width for two different PG depths. (a) Influences of TG2 on BV and Ron,sp. (b) Influences of TG3 on BV and FOM. Fig. 11. Gate charge with a turn-on voltage of 60 V and the device length of 4 μm. The inset on the left is the gate charge test circuit, and the right side is the TG LT LDMOS, SSG LT LDMOS on-state simulation. Fig. 13. Ron,sp versus the BV for SSG LT LDMOS and other different types of LDMOS.