Data for: Investigation of the Stepped Split Protection Gate L-Trench SOI LDMOS with Ultra-Low Specific On-Resistance by Simulation

Fig.3. Output capacitance versus effective gate voltage, VG-VT. Fig. 4. Comparison of transfer characteristics among the three structure at Vds = 25 V. Fig. 5. Thermal characteristics curves of (a) Con. LDMOS, TG LT LDMOS, and SSG LT LDMOS surface temperature characteristics along the drift region. (b) Temperature as a function of Tox thickness variation. Fig. 6. The relationship between drain voltage and current at breakdown. equi-potential contours of three devices, the proposed device, BV = 117 V, Con. LDMOS, BV = 101 V and TG LT LDMOS, BV = 102 V is shown as an insert. Fig. 7. The dependence of the Nd as a function of the BV and Ron,sp. Fig. 8. shows the influence of the Wt on the BV and FOM of the SSG LT LDMOS. The inset shows the effect of the left trench width on the BV of the device. Fig. 9. The effect of the thickness variation of the buried oxide layer on the BV of the device at the breakdown (a) The effect of Tox thickness variation on BV (Wt=0.5µm). (b) The charge concentration on both sides of the buried oxide layer corresponding to different buried layer thicknesses. Fig. 10. BV, Ron,sp and FOM of SSG LT LDMOS versus PG oxide width for two different PG depths. (a) Influences of TG2 on BV and Ron,sp. (b) Influences of TG3 on BV and FOM. Fig. 11. Gate charge with a turn-on voltage of 60 V and the device length of 4 μm. The inset on the left is the gate charge test circuit, and the right side is the TG LT LDMOS, SSG LT LDMOS on-state simulation. Fig. 13. Ron,sp versus the BV for SSG LT LDMOS and other different types of LDMOS.图3：输出电容与有效栅极电压V_G-V_T的关系曲线。图4：三种器件结构在漏源电压V_ds=25V时的转移特性对比。图5包含两组热特性曲线：(a) 常规横向双扩散金属氧化物半导体（Con. LDMOS）、沟槽栅极横向双扩散金属氧化物半导体（TG LT LDMOS）与自对准沟槽栅极横向双扩散金属氧化物半导体（SSG LT LDMOS）的漂移区表面温度特性；(b) 器件温度随氧化层厚度（Oxide Thickness，Tox）变化的关系曲线。图6展示了击穿工况下漏极电压与电流的关系，同时内嵌了三种器件的等势线分布：所提出的新型器件击穿电压（Breakdown Voltage，BV）为117V，常规LDMOS的BV为101V，TG LT LDMOS的BV为102V。图7为掺杂浓度N_d随击穿电压BV与比导通电阻（Specific On-Resistance，Ron,sp）变化的依赖关系曲线。图8展示了沟槽宽度W_t对SSG LT LDMOS的击穿电压BV与品质因数（Figure of Merit，FOM）的影响，内嵌部分为左侧沟槽宽度对器件击穿电压BV的影响效果。图9为击穿工况下埋氧层厚度变化对器件BV的影响，包含两组子图：(a) 当W_t=0.5μm时，氧化层厚度（Oxide Thickness，Tox）变化对BV的影响；(b) 对应不同埋层厚度的埋氧层两侧电荷浓度分布。图10为在两种不同多晶硅栅（Polysilicon Gate，PG）深度下，SSG LT LDMOS的BV、Ron,sp与PG氧化层宽度的变化关系，包含两组子图：(a) TG2对BV与Ron,sp的影响；(b) TG3对BV与FOM的影响。图11为导通电压60V、器件长度4μm时的栅极电荷特性曲线，左侧内嵌图为栅极电荷测试电路，右侧为TG LT LDMOS与SSG LT LDMOS的导通态仿真结果。图13为SSG LT LDMOS与其他不同类型LDMOS的比导通电阻Ron,sp随击穿电压BV变化的关系曲线。