Enhancing the Lifetimes of Complementary MEMS Logic Gates by Mitigation of Unwanted Capacitive Charging\/Discharging Data

In complementary MEMS logic gates, extremely low leakage currents have been viewed as an advantage over CMOS.  However, charging device terminals in high-voltage operation causes damaging current discharges that lead to contact failure.  This study presents a novel solution using a back-gate terminal through the handle layer of SOI wafers to preemptively charge\/discharge nominally insulated drain terminals.  By introducing controlled leakage paths via ALD-deposited TiN, terminals are discharged within the actuation window, significantly reducing transient currents and extending device lifetime.  The intentional introduction of leakage currents comes with the key tradeoff that with a decreased pad to handle layer resistance, an increasingly prominent voltage drop is observed across the actuating contacts as they degrade upon repeated use, negatively affecting operation.  Subsequently, devices are optimized to maximize operational lifetimes in terms of number of cycles.  Testing optimized devices revealed that decreasing the device to handle layer resistance from ~2 P\u2126 to ~50 G\u2126 with the conductive TiN conformal coating, increased the lifetime by 3 orders of magnitude, to 200k cycles.  Lifetimes were further increased by supplying a variable back gate voltage to further reduce power dissipated across the contacts, and by depositing 15 nm of graphite on the contact surface to improve durability.  These methods combined produce lifetimes of 760 k cycles on average \u2014 a four-order improvement over prior designs.  These innovations pave the way for viable asynchronous MEMS logic systems.