Large Rewriter Benchmark
收藏arXiv2025-09-30 收录
下载链接：
https://github.com/yaoxufeng/RTLRewriter-Bench
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资源简介：
该数据集是一个针对复杂场景的基准测试套件，包含了广泛的电路分割、优化权衡以及验证挑战。它源自对内部工业文档和关于寄存器传输级（RTL）优化学术文章的全面审查，包含了真实世界场景及其优化解决方案。该数据集的规模在于处理具有广泛分割的复杂场景，其任务重点是寄存器传输级代码优化。
This dataset is a benchmark suite targeting complex scenarios, which encompasses a wide range of circuit partitioning, optimization trade-offs, and verification challenges. It is derived from a comprehensive review of internal industrial documents and academic articles on register-transfer level (RTL) optimization, and includes real-world scenarios along with their corresponding optimization solutions. The dataset is designed to handle complex scenarios with extensive partitioning, and its core tasks focus on register-transfer level code optimization.
提供机构：
Experienced Verilog engineers
