TSMC 22nm工艺宽电压基础单元设计与测试数据

本数据集是基于TSMC22nm先进工艺节点构建的宽电压基础单元设计与测试基准数据集，旨在为宽电压基础单元设计、实现研究提供经过流片级工艺验证的标准参考资源。数据集的核心内容涵盖了工作电压跨度从0.6VDD至1.2VDD的常用标准单元列表及四种关键SRAM存储器，其规格包括64×128bit与1024×128bit的单端口SPRAM，以及32×72bit与128×64bit的双端口RF2PRAM。本数据集的数据结构依据工业界标准的后端设计流程进行组织，主要包含五类SRAM存储器关键设计与验证数据：一是用于版图与原理图一致性检查及电路级仿真的CDL网表文件；二是描述物理边界与金属层信息的LEF设计规则文件；三是最终制造所需的GDSII版图文件；四是覆盖多种PVT Corner条件的LIB单元库文件，用于逻辑综合与静态时序分析；五是基于实际测试生成的mt0仿真数据文件，记录了详细的性能指标。此外，数据集还附带了配套使用的组合逻辑单元与时序逻辑单元列表，确保设计环境的完整性。本数据集的使用面向高性能计算与低功耗芯片设计领域，支持用户在Linux环境下配合主流EDA工具链进行调用。通过使用本数据集，研究人员可系统评估宽电压设计技术在先进工艺下的时序收敛性、功耗表现及面积效率，并为相关科研项目提供了高可靠性的IP核资源。该数据集已作为重点研发计划项目成果的重要组成部分，进行规范化汇交与管理。

This dataset is a design and test benchmark dataset for wide-voltage basic cells built based on the TSMC 22nm advanced process node, aiming to provide standard reference resources that have undergone tape-out-level process verification for research on wide-voltage basic cell design and implementation. The core content of the dataset covers a list of common standard cells with operating voltage ranging from 0.6VDD to 1.2VDD, and four key SRAM memory devices. Their specifications include 64×128bit and 1024×128bit single-port SPRAM, as well as 32×72bit and 128×64bit dual-port RF2PRAM. The data structure of this dataset is organized in accordance with the industry-standard back-end design flow, and mainly includes five types of key design and verification data for SRAM memories: 1) CDL netlist files for layout-versus-schematic (LVS) checks and circuit-level simulation; 2) LEF design rule files describing physical boundaries and metal layer information; 3) GDSII layout files required for final manufacturing; 4) LIB cell library files covering multiple PVT Corner conditions, which are used for logic synthesis and static timing analysis (STA); 5) mt0 simulation data files generated based on actual tests, which record detailed performance metrics. In addition, the dataset also includes supporting combinational logic cell and sequential logic cell lists to ensure the completeness of the design environment. This dataset is targeted at high-performance computing and low-power chip design fields, and supports users to call it with mainstream EDA toolchains in a Linux environment. By using this dataset, researchers can systematically evaluate the timing closure, power performance and area efficiency of wide-voltage design technologies under advanced processes, and provide highly reliable IP core resources for relevant research projects. This dataset has been standardized, submitted and managed as an important part of the achievements of key research and development plan projects.

搜集汇总

背景与挑战

背景概述

该数据集是基于TSMC 22nm工艺节点构建的宽电压基础单元设计与测试基准数据集，包含工作电压跨度从0.6VDD至1.2VDD的常用标准单元列表及四种关键SRAM存储器，适用于高性能计算与低功耗芯片设计领域。数据集提供了多种设计与验证数据，支持研究人员在Linux环境下使用主流EDA工具链进行调用。