Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi2Te3 Thermoelectric Interfacial Layer

This document shows time-domain thermoreflectance (TDTR) measurements on blanket phase change multilayers [Fig. S1] and electro-thermal simulations of confined PCM cells [Fig. S2]. The extracted thermal resistance per unit area obtained from our measured TDTR signal ratio vs. time delay in Fig. S1 reveals that Bi2Te3 layer only introduces ~13% additional thermal resistance in the PCM stack. On the other hand, Fig. S2 shows the electro-thermal simulation of confined cells with 4 nm Bi2Te3 and 50 nm GST layer with a BE (TiN) diameter of 150 nm in Fig. S2(a) and control device with only 50 nm GST layer in Fig. S2(b). Simulations suggest that confined cell devices have ~20% lower Jreset compared to mushroom cell devices shown in the main text Fig. 4.

本文件展示了针对毯状相变多层结构的时域热反射率（TDTR）测量结果[图S1]以及封装相变存储单元（PCM）的电热仿真[图S2]。由图S1中的测量得到的TDTR信号比率与时间延迟的关系中提取的每单位面积热阻表明，Bi2Te3层仅在PCM堆叠中引入了约13%的额外热阻。另一方面，图S2展示了包含4 nm Bi2Te3层和50 nm GST层的封装单元的电热仿真，其中图S2(a)展示了具有150 nm BE（TiN）直径的控制设备，图S2(b)展示了仅包含50 nm GST层的对照设备。仿真结果表明，与正文图4中展示的蘑菇状单元设备相比，封装单元设备具有约20%的更低Jreset值。