"CORE - Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research"
收藏DataCite Commons2025-06-25 更新2026-05-03 收录
下载链接：
https://ieee-dataport.org/documents/core-corpus-synthesizable-verilog-rtl-modules-dataset-eda-research
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资源简介：
"This repository contains a comprehensive collection of parameterized and configurable RTL modules written in Verilog, organized by category for EDA research and development. Each module is thoroughly verified and comes with complete testbenches and detailed documentation to support efficient integration and use."
提供机构：
IEEE DataPort
创建时间：
2025-06-25
