"A Pipelined Compute-in-Memory Architecture for High-Efficiency MAC Array in Neuromorphic chip"
收藏DataCite Commons2025-11-14 更新2026-05-03 收录
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https://ieee-dataport.org/documents/pipelined-compute-memory-architecture-high-efficiency-mac-array-neuromorphic-chip
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资源简介：
"Subject: A Pipelined In-Memory Computing Architecture for Energy-Efficient MAC Arrays in Neuromorphic ChipsCore Innovations:1.Multi-Level Pipelined In-Memory Computing ArchitectureComparison of various computing array configurations: 2D TianjicX, 3D (4\u00d72\u00d716), and 3D (4\u00d74\u00d78).Under a 192KB memory constraint, the 3D architecture achieves 80.39% peak efficiency, significantly outperforming the 2D architecture's 79.83%.2.Dynamic Memory-Aware Mapping StrategyAs memory capacity increases from 64KB to 512KB, computational efficiency improves from 12.35% to 91.23%.A memory-sensitive data reuse scheme is proposed, reducing inter-cluster routing overhead by 66%.3.Heterogeneous Data Flow OptimizationAt an input depth of 256, the 3D architecture achieves 86.49% efficiency, a 12.5% improvement over the 2D architecture.Pipeline parallelism between computation and transmission is achieved through output channel partitioning (32\u219216\u21928)."
提供机构：
IEEE DataPort
创建时间：
2025-11-14
