"Neuromorphic_4Bit_Adder_CMOS"
收藏DataCite Commons2025-09-30 更新2026-05-03 收录
下载链接：
https://ieee-dataport.org/documents/neuromorphic4bitaddercmos
下载链接
链接失效反馈官方服务：
资源简介：
"This dataset contains simulation schematics, layout files, and benchmarking results for RCA, CLA, and TLA adder architectures. It includes DSCH schematic files and MicroWind layout designs, along with tabulated performance metrics for delay, power, and area. The data supports reproducibility and comparative analysis of threshold logic-based neuromorphic designs, and complements the findings presented in the associated manuscript."
提供机构：
IEEE DataPort
创建时间：
2025-09-30
