A scalable superconducting nanowire memory array with row-column addressing

Figure 1. Device architecture and operation concept of the superconducting nanowire memory (SNM). This figure illustrates the structure and operating principle of the SNM cell. It includes a schematic representation of the nanowire circuit layout, highlighting key components such as the storage loop, write and read paths, and control lines. The figure also includes a simplified circuit diagram and a conceptual illustration of the bistable states corresponding to stored logical ‘0’ and ‘1’. These states are defined by the presence or absence of a persistent current in the storage loop, enabling non-volatile memory behavior.