36-Bit Minicomputer Using SRAM ICs as Logic Elements

This is a design-in-progress for a 36-bit, 20 MIPS, open-source minicomputer that uses synchronous static RAM ICs as logic elements, plus a minimal amount of glue logic. This dataset contains netlists, firmware, a virtual machine for simulating the ALU, a discrete event simulator for simulating the entire computer with wire delays, an assembler, a circuit board layout, and software written in C and Python for producing all of the foregoing. A Ph.D. dissertation that describes and documents this work is included as a separate file. Significant portions of this work in simulation correctly, but the entire machine is not yet something that can be built in operable form.