36-Bit Minicomputer Using SRAM ICs as Logic Elements

This is a design-in-progress for a 36-bit, 20 MIPS, open-source minicomputer that uses synchronous static RAM ICs as logic elements, plus a minimal amount of glue logic. This dataset contains netlists, firmware, a virtual machine for simulating the ALU, a discrete event simulator for simulating the entire computer with wire delays, an assembler, a circuit board layout, and software written in C and Python for producing all of the foregoing. A Ph.D. dissertation that describes and documents this work is included as a separate file. Significant portions of this work in simulation correctly, but the entire machine is not yet something that can be built in operable form.本项目为一款处于研发阶段的36位、20百万条指令每秒（MIPS）开源小型计算机，其采用同步静态随机存取存储器集成电路（synchronous static RAM ICs）作为逻辑核心元件，并搭配少量胶合逻辑电路（glue logic）。本数据集包含网表（netlists）、固件（firmware）、用于模拟算术逻辑单元（ALU, Arithmetic Logic Unit）的虚拟机、支持连线延迟仿真的整机离散事件模拟器、汇编器（assembler）、电路板布局文件，以及用于生成上述所有内容的C语言与Python语言开发的配套软件。另有一份对本项目进行详细阐述与归档的博士学位论文，以独立文件形式随附于本数据集。本项目的多数仿真模块均可正确运行，但整机仍未达到可正常制造并投入实用的成熟状态。