Phonon-limited mobility for electrons and holes in highly-strained silicon

Strain engineering is a widely used technique for enhancing the mobility of charge carriers in semiconductors, but its effect is not fully understood. In this work, we perform first-principles calculations to explore the variations of the mobility of electrons and holes in silicon upon deformation by uniaxial strain up to 2% in the [100] crystal direction. We compute the π₁₁ and π₁₂ electron piezoresistances based on the low-strain change of resistivity with temperature in the range 200 K to 400 K, in excellent agreement with experiment. We also predict them for holes which were only measured at room temperature. Remarkably, for electrons in the transverse direction, we predict a minimum room-temperature mobility about 1200 cm²/Vs at 0.3% uniaxial tensile strain while we observe a monotonous increase of the longitudinal transport, reaching a value of 2200 cm²/Vs at high strain. We confirm these findings experimentally using four-point bending measurements, establishing the reliability of our first-principles calculations. For holes, we find that the transport is almost unaffected by strain up to 0.3% uniaxial tensile strain and then rises significantly, more than doubling at 2% strain. Our findings open new perspectives to boost the mobility by applying a stress in the [100] direction. This is particularly interesting for holes for which shear strain was thought for a long time to be the only way to enhance the mobility.

晶格工程作为一种广泛应用于提升半导体中电荷载体迁移率的常用技术，其作用机制尚未得到充分理解。本研究中，我们通过一阶原理计算，探究了硅在单轴应变至2%的[100]晶向变形下，电子与空穴迁移率的变异情况。基于200至400 K温度范围内电阻率对低应变变化的响应，我们计算了π₁₁和π₁₂电子压阻系数，其结果与实验数据高度吻合。同时，我们针对室温下仅测量到的空穴进行了预测。令人瞩目之处在于，对于横向的电子，我们预测在0.3%的单轴拉伸应变下，室温迁移率将达到约1200 cm²/Vs，而纵向传输则随着应变的增加呈单调上升，在较高应变下达到2200 cm²/Vs。我们通过四点弯曲测量实验验证了这些发现，从而确立了本征原理计算的可信度。对于空穴，我们发现，在0.3%的单轴拉伸应变范围内，传输几乎不受应变影响，但在2%应变时显著上升，增幅超过一倍。我们的研究为通过在[100]方向施加应力来提升迁移率开辟了新的视野。这对长期以来被认为只能通过剪切应变来提升空穴迁移率的观点提出了新的挑战。