Characterization-History Dependence of Threshold-Voltage Sensitivity in NOR2 Gate Chains

This dataset provides the simulation data and reproducibility materials accompanying the research study “Characterization-History Dependence of Threshold-Voltage Sensitivity in NOR2 Gate Chains.” The study investigates how threshold-voltage sensitivity depends on the characterization history of seven-stage CMOS NOR2 and NAND2 gate chains, using 45-nm and 65-nm predictive technology models (PTM). It compares first-switching (E1) and fourth-crossing periodic (IS) conditions across 96 circuit configurations and evaluates delay-increment predictions against 480 full-SPICE reference records. The archive includes 19 electronic supplementary CSV tables, additional nominal-delay baselines, per-transistor sensitivity and prediction records, numerical verification data, selected internal-node waveform data, uniform multi-device threshold-voltage perturbation results, and input-slew–load characterization results. Reproducibility materials include Python analysis and plotting scripts, figure-source data, reference figures, 96 topology netlists without third-party PTM model libraries, documentation, and file-integrity information. The provided threshold-voltage perturbations represent controlled numerical scenarios, not silicon-calibrated BTI lifetime predictions. The designated test set is reported as non-blind. Reproducing transistor-level simulations requires obtaining the appropriate third-party PTM models separately. The accompanying README provides details of the file organization, analysis procedures, and methodological limitations. The same SCI2 dataset is also archived in IEEE DataPort under DOI: 10.21227/k9j4-p590 (https://doi.org/10.21227/k9j4-p590). This Zenodo record provides a freely accessible distribution of the research data and reproducibility materials.