CORE - Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research

Name: CORE - Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research
Creator: Harikrishnan Ramiah; Yongfu Li; Yuxin Ji; Kian Kit Cheah; Fu Qi Chua; Zhuofan Lin; YunXiang Zhang; Xinfei Guo
Published: 2026-04-17T17:24:52+08:00

IEEE2026-04-17 收录

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数据链接：

https://ieee-dataport.org/documents/core-corpus-synthesizable-verilog-rtl-modules-dataset-eda-research 数据链接链接失效反馈

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资源简介：

This repository contains a comprehensive collection of parameterized and configurable RTL modules written in Verilog, organized by category for EDA research and development. Each module is thoroughly verified and comes with complete testbenches and detailed documentation to support efficient integration and use.

提供机构：

Harikrishnan Ramiah; Yongfu Li; Yuxin Ji; Kian Kit Cheah; Fu Qi Chua; Zhuofan Lin; YunXiang Zhang; Xinfei Guo

CORE - Corpus of Synthesizable Verilog RTL Modules Dataset for EDA Research

资源简介：

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