高性能忆阻神经形态器件与芯片数据集

本数据集涵盖了2022年1月至2025年11月期间，由之江实验室与工业和信息化部电子第五研究所联合采集的高性能忆阻神经形态芯片全流程数据。研究采用“材料-器件-电路-芯片-系统-应用”多层级实测方案，利用半导体参数分析仪针对基于HfOx的忆阻器与基于NbOx的神经元器件和阵列进行电学特性测定；针对芯片阵列规模，借助扫描电镜（scanning electron microscopy, SEM）、聚焦离子束（focused ion beam, FIB）及半自动探针台进行纳米级形貌表征与电学测量。在电路与架构层面，基于Linux服务器环境利用电子设计自动化（electronic design automation, EDA）工具完成设计与规则检查；系统验证环节则通过现场可编程逻辑门阵列（field programmable gate array, FPGA）开发板、示波器等搭建硬件测试平台，实测验证存算一体阵列的读、写功能。此外，通过部署图计算、模式识别等典型应用场景，对芯片在实际执行任务中的计算性能与算法支撑能力进行了全面的功能测试。本数据集为新型存算一体芯片的研发提供了全栈式的实测参考，对推动低功耗高性能存算一体硬件的产业化落地具有重要意义。This dataset contains full-process data of high-performance memristive neuromorphic chips jointly collected by Zhejiang Lab and the Fifth Electronics Research Institute of the Ministry of Industry and Information Technology (MIIT) from January 2022 to November 2025. The research adopts a multi-level practical measurement scheme following the "material-device-circuit-chip-system-application" hierarchy, where electrical characteristics of HfOₓ-based memristors and NbOₓ-based neuronal devices and arrays are measured using a semiconductor parameter analyzer. For chip arrays, nanoscale morphological characterization and electrical measurements are conducted via scanning electron microscopy (SEM), focused ion beam (FIB), and semi-automatic probe stations. At the circuit and architecture level, design and rule checks are completed using electronic design automation (EDA) tools in a Linux server environment. In the system validation stage, a hardware test platform is built with field programmable gate array (FPGA) development boards, oscilloscopes and other equipment to experimentally verify the read and write functions of the in-memory computing array. Furthermore, typical application scenarios such as graph computing and pattern recognition are deployed to conduct comprehensive functional tests on the chip's computing performance and algorithm support capabilities during actual task execution. This dataset provides a full-stack practical measurement reference for the R&D of novel in-memory computing chips, and is of great significance for promoting the industrial implementation of low-power, high-performance in-memory computing hardware.

搜集汇总

背景与挑战

背景概述

该数据集汇集了2022年至2025年期间由之江实验室与工信部电子五所联合采集的高性能忆阻神经形态芯片全流程数据，通过材料、器件、电路到系统的多层级实测方案，涵盖了电学特性、形貌表征、设计验证及功能测试。它为新型存算一体芯片的研发提供了全栈式实测参考，对推动低功耗高性能硬件的产业化具有重要意义。