All project data

In this work, we simplify the update rules and the associated circuitry for probabilistic computers emulated on a field-programmable gate array. We test our simplifications through the lens of smaller logic gates as well as integer factorization of various sizes.本研究简化了在现场可编程门阵列（field-programmable gate array，FPGA）上仿真实现的概率计算机的更新规则与相关电路，并以小型逻辑门以及不同规模的整数分解任务为测试对象，对上述简化方案开展了验证工作。