Data and code underlying the research of: Robust logic for STT based CIM

This work targets BNN-related applications. Given the inherent low sensing margins due to low TMR of STT devices, this work proposes an adaptive referencing mechanism to improve the sensing margin while performing logic operations in an STT-MRAM-based CIM. Reference signals are generated using multiple STT-MRAM devices and placed strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. The concept is demonstrated using an STT-MRAM model, which is calibrated using 1Mb characterized array at IMEC and is validated by deploying it in a BNN. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

本研究聚焦于二元神经网络（Binary Neural Network，BNN）相关应用。鉴于自旋转移矩（Spin-Transfer Torque，STT）器件的隧道磁电阻（Tunnel Magnetoresistance，TMR）较低，固有传感裕度不足，本研究提出一种自适应参考机制，在基于自旋转移矩磁随机存取存储器（Spin-Transfer Torque Magnetic Random-Access Memory，STT-MRAM）的计算内存（Compute-in-Memory，CIM）中执行逻辑运算的同时，提升传感裕度。该机制通过多颗STT-MRAM器件生成参考信号，并将其合理布局于阵列中，可有效应对工艺波动并追踪布线寄生参数。本研究采用STT-MRAM模型验证该概念，该模型通过微电子研究中心（Interuniversity Microelectronics Centre，IMEC）的1Mb表征阵列完成校准，并通过在BNN中部署该模型实现有效性验证。本数据集包含原理图网表文件、用于延迟与功耗估算及仿真结果的Excel原始数据表，以及用于生成相关发表论文中图表的Matlab代码。