Advanced Ferroelectric Field Effect Transistors for Memory and AI Applications

In the past decades, the demand for high-performance large-capacity memory technologies has been arisen quickly due to the rapid growth of data generation. To address this challenge, researchers and engineers are actively exploring emerging memory devices and novel architectures, to overcome "the memory wall" problem. Among these, ferroelectric field effect transistors (FeFETs) have gained significant attention as a promising candidate for large-capacity high-performance storage and compute-in-memory. Hf0.5Zr0.5O2 based FeFETs offer substantial advantages, including energy efficiency, long retention, and fast operating speed. Moreover, the well-established high-k HfO2 fabrication technology and low operating voltage make Hf0.5Zr0.5O2 based FeFETs highly compatible with existing CMOS manufacturing processes, facilitating their integration into next-generation memory and computing systems.

In this report, a FeFET process integration flow is proposed. Layout design, fabrication techniques, and device characterizations are discussed. Applications in secure storage, compute-in-memory, spatial-temporal sequence detection are experimentally demonstrated. To enhance the memory window and achieve multi-level storage, a charge-trapping layer is introduced onto the ferroelectric layer to induce gate-side injection. Various configurations of the charge-trapping layers are investigated to compare their performance. Large-memory-window FeFETs are experimentally demonstrated.

Read/pass disturb is one of the main challenges FeFETs are facing when used as a storage solution. Long-term stress applied to FeFETs can disturb the high-VTH state, leading to data loss. The origin of the read disturb issue is explored by analyzing the correlations between the external electric field and internal ferroelectric polarization. Solutions for the pass disturb-free operations are also proposed and experimentally validated.

Finally, future work is outlined to guide further exploration. A double-gate, pass disturb-free, large-memory-window FeFET for vertical NAND storage is presented, along with detailed designs and feasibility studies. Current progress on the device fabrication and characterizations are also reported.

近数十年来，随着数据生成量的飞速增长，对高性能大容量存储技术的需求迅速攀升。为应对这一挑战，研究人员与工程师正积极探索新型存储器件与架构，以破解“内存墙”难题。其中，铁电场效应晶体管（FeFETs）作为大容量高性能存储与存算一体的极具潜力的候选方案，受到了广泛关注。基于Hf₀.₅Zr₀.₅O₂的铁电场效应晶体管拥有诸多显著优势，包括能效出色、数据保留时长优异以及运行速度迅捷。此外，成熟的高k HfO₂制备工艺以及低工作电压，使得基于Hf₀.₅Zr₀.₅O₂的铁电场效应晶体管与现有CMOS制造工艺具备高度兼容性，便于其集成至下一代存储与计算系统中。

本报告提出了一种FeFET工艺集成流程，并对版图设计、制备工艺以及器件表征展开讨论。同时，通过实验验证了其在安全存储、存算一体以及时空序列检测领域的应用。为拓宽存储窗口并实现多级存储，本研究在铁电层上引入电荷捕获层以诱导栅侧注入。研究了多种电荷捕获层结构以对比其性能表现，并通过实验实现了具备大存储窗口的FeFETs。

作为存储解决方案时，读/通行干扰是FeFETs面临的主要挑战之一。对FeFETs施加的长期应力会干扰高阈值电压（VTH）状态，进而导致数据丢失。本研究通过分析外部电场与内部铁电极化之间的关联，探究了读干扰问题的根源。同时，提出了无通行干扰运行的解决方案，并通过实验验证了其有效性。

最后，本报告概述了后续研究方向以指导进一步探索。提出了一种面向垂直NAND存储的双栅极、无通行干扰、大存储窗口FeFET，附带详细的设计方案与可行性分析，同时汇报了该器件在制备与表征方面的最新进展。