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RCQ LDPC Decoding with Degree-Specific Neural Edge Weights

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DataCite Commons2024-01-09 更新2025-04-16 收录
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http://dataverse.jpl.nasa.gov/citation?persistentId=doi:10.48577/jpl.7FIYNV
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A reconstruction-computation-quantization (RCQ) decoder for low-density parity-check (LDPC) code uses dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. The quantization and reconstruction tables for RCQ decoders are updated in each layer and each iteration, which requires considerable look-up table (LUT) utilization that may offset the LUT saving by passing low-bit-width messages. The main contribution of this paper is a weighted RCQ (W-RCQ) decoding structure with reduced LUT utilization and similar FER performances compared with the original RCQ decoder designs. W-RCQ decoder differs RCQ decoder in two ways: First, W-RCQ uses fewer quantizer/dequantizer pairs, and each pair is responsible for several iterations; Second, the check-to-variable messages in W-RCQ decoder are weighted by multiplicative or additive parameters that are optimized via a quantized neural network (QNN). These parameters can be shared by messages from different levels, such as node-degree or circulant levels, with different resource usages. Our simulation result for a (9472,8192) LDPC code on a field-programmable gate array (FPGA) device shows that the 4-bit W-RCQ decoder delivers comparable FER performance but with much fewer hardware resources, compared with the 4-bit RCQ decoder and the 5-bit offset MinSum decoder.

针对低密度奇偶校验码(low-density parity-check, LDPC)的重构-计算-量化(reconstruction-computation-quantization, RCQ)解码器,采用动态非均匀量化技术,可在极低消息精度下实现优异的误帧率(frame error rate, FER)性能。RCQ解码器的量化与重构表会在每一层、每一次迭代中更新,这需要占用大量查找表(look-up table, LUT)资源,甚至可能抵消因传递低比特宽度消息所节省的LUT资源。本文的主要贡献在于提出了加权重构-计算-量化(W-RCQ)解码架构,该架构在降低LUT资源占用的同时,可实现与原始RCQ解码器设计相当的FER性能。W-RCQ解码器与RCQ解码器存在两点差异:其一,W-RCQ使用更少的量化器/反量化器对,且每个量化器/反量化器对可负责多次迭代;其二,W-RCQ解码器中的校验节点到变量节点的消息,由通过量化神经网络(quantized neural network, QNN)优化得到的乘性或加性参数进行加权。这些参数可由不同层级(如节点度或循环移位层级)的消息共享,同时适配不同的资源占用需求。针对(9472,8192) LDPC码在现场可编程门阵列(field-programmable gate array, FPGA)上的仿真结果表明,相较于4位RCQ解码器与5位偏移最小和(offset MinSum)解码器,4位W-RCQ解码器可在FER性能相当的前提下,硬件资源占用大幅降低。
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Root
创建时间:
2024-01-07
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