A delay efficient hybrid parallel prefix variable latency CSKA based multi-operand adder with optimized 5:2 compressor and skip logic

In this paper, a delay efficient multi-operand adder (MOA) is introduced by considering the compression logic and variable latency carry skip adder (VL-CSKA). Here, an optimised 5:2 compressor is initially used to increase the speed of MOA by reducing the number of operands before giving as input to VL-CSKA. Also, the VL-CSKA is modified by replacing the carry propagation with complementary complex gates (CCG) and nucleus stage with improved parallel prefix structure for increasing the speed with fewer components. The delay, area, power and logic depth of the proposed hybrid parallel prefix VL-CSKA (HPP-VL-CSKA) is also reduced by modifying the group Propagate–Generate (PG) logic in the parallel prefix structure. Also, a new circuit for XOR/XNOR gate is used for the reduction of the delay and power consumption significantly. The synthesis result shows that the suggested adder design overtakes the existing adders by consuming only 5953µm2 area, 1.763mW power, 1.251fJ and 3516.63 ADP for 20 number of operands, each with 32 bit inputs.本文提出一种时延高效多操作数加法器（multi-operand adder, MOA），其构建基于压缩逻辑与可变时延进位跳过加法器（variable latency carry skip adder, VL-CSKA）。本文首先采用优化后的5:2压缩器，在将操作数输入VL-CSKA前先减少操作数数量，以此提升MOA的运算速度。此外，本文对VL-CSKA进行改进：将进位传输路径替换为互补复合门（complementary complex gates, CCG），并将核心级替换为改进型并行前缀结构，从而在减少元器件数量的同时提升运算速度。同时，通过修改并行前缀结构中的组传输-生成（group Propagate–Generate, PG）逻辑，所提出的混合并行前缀可变时延进位跳过加法器（hybrid parallel prefix VL-CSKA, HPP-VL-CSKA）的时延、芯片面积、功耗与逻辑深度均得以降低。此外，本文采用一种新型异或/同或门电路，可显著降低运算时延与功耗。综合结果表明，在20个32位输入操作数的场景下，所提出的加法器设计性能优于现有加法器，其芯片面积仅为5953 µm²，功耗为1.763 mW，单位能耗为1.251 fJ，面积时延积（Area-Delay Product, ADP）为3516.63。