Data and code underlying the research of: CCO-ADC for CIM Acclerators

This targets image classification applications. This work presents a memory-periphery co-design to perform accurate A/D conversions of analog matrix-vector-multiplication (MVM) outputs. A novel scheme is introduced where select-lines and bit-lines in the memory are virtu- ally fixed to improve conversion accuracy and aid a ring-oscillator-based A/D conversion, equipped with component sharing and inter-matching of the reference blocks. In addition, we deploy a self-timed technique to further ensure high robustness addressing global design and cycle-to-cycle variations. The concept is demonstrated using a 4Kb CIM chip prototype using resistive bitcells on TSMC 40nm CMOS technology. This dataset includes schematic netlist files, chip photos, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.

本数据集面向图像分类应用场景。本研究提出一种存储-外设协同设计方案，可对模拟矩阵向量乘法（Matrix-Vector-Multiplication，MVM）的输出信号实现高精度模数转换。本方案引入一项新型设计：将存储器内的选择线与位线进行虚拟固定，以提升转换精度并辅助基于环形振荡器的模数转换；该方案集成了组件共享与参考模块间的匹配校准机制。此外，本研究采用自定时技术，可进一步增强系统鲁棒性，有效应对全局设计偏差与周期间波动。本研究采用台积电40纳米CMOS工艺下的电阻型存储单元，搭建了4Kb计算存储（Compute-in-Memory，CIM）芯片原型以验证该设计理念。本数据集包含原理图网表文件、芯片实拍照片、用于延迟与功耗估算及仿真结果的Excel原始数据表，以及用于生成相关学术论文中图表的Matlab代码。