Iontronic memristor logic gate voltage curves

Input and output voltages, as well as simulation parameters for logic gates based on iontronic memristors and shinriki-inspired oscillators.

Data was generated with the simulation code code.

Data is stored as .jld2-files. It julia data structures in a subset of the HDF5 specification.

Data for voltage current curves of single memristors for 0.4Hz 40Hz and 400Hz driving frequency is in the directory memristor.

Oscillation data for single memriki oscillators can be found in the directory dynamics. It shows simples oscillation, a subharmonic response, and chaotic behavior, depending on the driving frequency and a tunable resistance.

The the single-gates directory contains input output voltage curves for XOR and NAND (pre) logic gates. 

Voltage input output curves for AND and OR gates comprised from three NAND gates.

100 iterations of all logic levels for all the implemented logic gates can be found in the repeatability directory.

本数据集包含基于离子忆阻器（iontronic memristors）与受shinriki启发的振荡器（shinriki-inspired oscillators）的逻辑门所需的输入输出电压及仿真参数。
数据集数据通过配套仿真代码生成。
数据以.jld2格式存储，其内部采用HDF5规范子集的Julia数据结构进行组织。
针对驱动频率分别为0.4Hz、40Hz与400Hz的单离子忆阻器伏安特性曲线数据，存储于memristor目录下。
单memriki振荡器的振荡数据存放于dynamics目录下，该数据可展现随驱动频率与可调电阻变化的简谐振荡、次谐波响应及混沌行为。
single-gates目录收录了异或（XOR）与与非（NAND，预配置版）逻辑门的输入输出电压曲线。
由三个与非（NAND）门搭建的与（AND）门及或（OR）门的输入输出电压曲线数据亦已收录。
所有已实现逻辑门的全部逻辑电平的100次重复测试数据，存储于repeatability目录中。