Table II UNIFORMITY OF TC-PUF DESIGN (For FPGA board No. 1 to 15)

This data set corresponds to Table II:UNIFORMITY OF TC-PUF DESIGN of manuscript titled "A Lightweight and Secure Physical Unclonable Function Design on FPGA".  The provided data is for FPGA board No. 1 to 15. Board no. 1 to 14  represent uniformity of 40X40 TC-PUF response implemented on Artix-7 FPGA, and board no. 15  represent uniformity of 20X40 TC-PUF response implemented on Zynq Z-7010 FPGA. It is observed that nearly all the TC-PUF implemented on individual FPGAs have a slight bias towards ‘0’. Although the value obtained is close to its ideal value, the value of obtained uniformity can be relaxed for our design since the acquired TC-PUF responses are fed to LFSR which overcomes the bias problem while expanding the PUF response.

本数据集对应题为《面向现场可编程门阵列（Field-Programmable Gate Array，FPGA）的轻量型安全物理不可克隆函数（Physical Unclonable Function，PUF）设计》的论文手稿中的表II：TC-PUF设计的均匀性。本次提供的数据对应编号1至15的FPGA开发板。编号1至14的开发板对应在Artix-7 FPGA上实现的40×40 TC-PUF响应的均匀性数据，编号15的开发板则对应在Zynq Z-7010 FPGA上实现的20×40 TC-PUF响应的均匀性数据。经观测发现，几乎所有在单块FPGA上实现的TC-PUF均存在向二进制‘0’轻微偏移的现象。尽管实测得到的均匀性数值接近理想值，但本设计的均匀性指标可适当放宽——这是因为采集得到的TC-PUF响应会被输入至线性反馈移位寄存器（Linear Feedback Shift Register，LFSR），该模块可在扩展PUF响应的同时解决偏移问题。