Table II UNIFORMITY OF TC-PUF DESIGN (For FPGA board No. 1 to 15)

This data set corresponds to Table II:UNIFORMITY OF TC-PUF DESIGN of manuscript titled A Lightweight and Secure Physical Unclonable Function Design on FPGA.  The provided data is for FPGA board No. 1 to 15. Board no. 1 to 14  represent uniformity of 40X40 TC-PUF response implemented on Artix-7 FPGA, and board no. 15  represent uniformity of 20X40 TC-PUF response implemented on Zynq Z-7010 FPGA. It is observed that nearly all the TC-PUF implemented on individual FPGAs have a slight bias towards ‘0’. Although the value obtained is close to its ideal value, the value of obtained uniformity can be relaxed for our design since the acquired TC-PUF responses are fed to LFSR which overcomes the bias problem while expanding the PUF response.