Repository for PromptRTL: Evaluating Prompt Engineering for Hardware Design
收藏Zenodo2025-03-15 更新2026-05-26 收录
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https://zenodo.org/doi/10.5281/zenodo.15029586
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资源简介：
Prompt RTL conducts a comprehensive evaluation of state-of-the-art prompt engineering techniques in the context of hardware design, with a specific focus on generating functional Verilog.
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Zenodo创建时间：
2025-03-15
