多工艺节点国产EDA验证数据集

本数据集来源于国家重点研发计划青年科学家项目“基于强化学习的布图规划设计方法研究”的研究结果。该数据集面向布图规划算法在业界实例中的泛化能力与工程适配能力评估，汇集了所提出算法集成至国产EDA工具Lecompiler后的运行数据。实验对象涵盖上海立芯科技提供的客户业界多种类型设计、不同工艺节点的12个国产数字集成电路实例，工艺节点覆盖28nm、14nm 及7nm。在数据采集过程中，将本项目实现的布图规划算法集成至上海立芯科技的EDA工具Lecompiler，首先采用本项目所实现的算法对上述业界实例进行布图规划实验，保存训练得到的模型，并执行国产EDA工具Lecompiler进行布图检查、后续布局及早期全局布线等验证流程，生成工具运行日志（log）文件。同时，数据集对实验过程中产生的布局相关信息进行结构化整理，形成统计汇总文件（csv），并提供算法训练得到的模型参数文件（pkl）及其加载脚本。该数据集可为本项目所提出的强化学习布图规划方法在不同工艺条件下的适应能力提供数据支撑。This dataset is derived from the research outcomes of the National Key R&D Program of China Young Scientist Project titled "Research on Floorplanning Design Methods Based on Reinforcement Learning". This dataset is intended for evaluating the generalization and engineering adaptation capabilities of floorplanning algorithms in real-world industrial scenarios, and compiles the operational data of the proposed algorithm after integration into the domestic EDA tool Lecompiler. The experimental subjects cover 12 domestic digital integrated circuit instances of various types and different process nodes provided by Shanghai Lixin Technology, with the process nodes ranging from 28nm, 14nm to 7nm. During data collection, the floorplanning algorithm developed in this project was integrated into the EDA tool Lecompiler provided by Shanghai Lixin Technology. First, floorplanning experiments were conducted on the aforementioned industrial instances using the algorithm developed in this project, the trained model was saved, and the domestic EDA tool Lecompiler was executed to carry out verification processes including floorplan checking, subsequent placement, and early global routing, generating tool run log files. Meanwhile, the dataset structurally organizes the layout-related information generated during the experiments to form a statistical summary file (CSV), and provides the model parameter file (PKL) obtained from algorithm training and its loading script. This dataset can provide data support for verifying the adaptation capability of the reinforcement learning-based floorplanning method proposed in this project under different process conditions.

搜集汇总

背景与挑战

背景概述

该数据集源自国家重点研发计划项目，用于验证强化学习布图规划算法在国产EDA工具Lecompiler中的泛化与工程适配能力。它涵盖28nm、14nm及7nm工艺节点的12个数字集成电路实例，包含工具运行日志、统计文件和模型参数等数据。