时序分析测试门级网表数据集

时序分析测试门级网表数据集主要用于高精度时序仿真分析测试。门级网表主要记录了数字电路设计过程中，编写完verilogHDL以后，通过逻辑综合生成的物理网表，网表里包括了基于晶圆厂提供的时序单元库所生成的各种组合电路、时序电路、时钟。数据量为435Kbyte。

The gate-level netlist dataset for timing analysis testing is primarily intended for high-precision timing simulation and analysis tests. Gate-level netlists in this dataset are physical netlists generated via logic synthesis after completing Verilog HDL coding during the digital circuit design process. They include various combinational circuits, sequential circuits, and clock signals created based on the timing standard cell libraries provided by semiconductor fabrication plants. The total data size of this dataset is 435 Kbytes.

搜集汇总

背景与挑战

背景概述

时序分析测试门级网表数据集主要用于高精度时序仿真分析测试，包含数字电路设计过程中通过逻辑综合生成的物理网表，涉及组合电路、时序电路和时钟等，数据量为435Kbyte。该数据集由南京华大九天科技有限公司创建，属于国家重点研发计划项目'超低电压高精度时序分析技术'的成果。