Modeling and testing crosstalk faults in arbitrary inter-core interconnects that include tri-state and bi-directional nets

Unrestricted The shrinking of the dimensions of on-chip interconnects (global interconnects, including inter-core interconnects in SOCs) due to advancements in VLSI fabrication process technologies exacerbates capacitive crosstalk and necessitates the testing of interconnects to ensure that each manufactured chip is free of excessive crosstalk. We demonstrate that vector pairs recommended by existing crosstalk fault model for interconnects may not excite the worst case severities of crosstalk effects in interconnects with arbitrary topologies. Moreover, no technique exists for testing crosstalk in interconnects that include tri-state and bi-directional nets.; In this dissertation, we start with a simulation study to (i) identify the factors that significantly affect the severities of crosstalk effects in arbitrary interconnects, (ii) demonstrate that crosstalk severity at a victim net is nearly independent of nets at level-k or higher with respect to the victim net, and (iii) demonstrate that previous crosstalk model does not necessarily invoke crosstalk effects with maximum severities.; We then develop the first approaches to compute bounds on the amplitude of crosstalk pulse. Our approaches can compute bounds for certain types of partially-specified vector pairs. The bounds we compute for a partially-specified vector pair are guaranteed to hold for all fully-specified vector pairs contained in that partially-specified vector pair. We use the computed bounds to select/eliminate vector pairs to be used for testing the interconnects.; We then develop the first crosstalk fault model for such interconnects. The vector pairs are divided into data vector pairs and control vectors. We identify the conditions that data vector pairs must satisfy to guarantee coverage. The requirements for control vectors are developed so as to (i) avoid circuit damage due to short circuit, (ii) minimize unnecessary yield loss, and (iii) minimize the size of the set of control vectors used during testing. We also develop techniques to minimize test vector pairs.; Finally, we develop a test generation framework including a representation for arbitrary interconnects. We use above techniques to minimize vector pairs. The experimental results demonstrate that our approach significantly reduces the test cost while guaranteeing safe testing and maximal test quality.无限制场景下，随着超大规模集成电路（VLSI，Very Large Scale Integration）制造工艺技术的进步，片上互连（on-chip interconnects，包括全局互连与系统级芯片（SOC，System on Chip）中的核间互连（inter-core interconnects））的尺寸持续缩小，这一现象加剧了电容串扰（capacitive crosstalk）问题，因此需对互连结构开展测试，以确保每一片量产芯片均不存在过度串扰。我们证实，现有互连串扰故障模型（crosstalk fault model）所推荐的向量对（vector pairs），未必能在任意拓扑结构的互连中激发最严重的串扰效应。此外，目前尚无适用于包含三态（tri-state）与双向网络（bi-directional nets）的互连结构的串扰测试技术。在本学位论文（dissertation）中，我们首先通过仿真研究（simulation study）完成三项工作：（i）明确显著影响任意互连结构中串扰效应严重程度的关键因素；（ii）验证了受害网络（victim net）的串扰严重程度与以该受害网络为基准的k级及更高级别网络几乎无关；（iii）证实了此前的串扰模型未必能触发最大严重程度的串扰效应。随后，我们提出了首批用于计算串扰脉冲幅度（amplitude of crosstalk pulse）边界的方法，该方法可针对特定类型的部分指定向量对（partially-specified vector pairs）计算边界值。我们所计算得到的边界，可确保对所有包含于该部分指定向量对中的全指定向量对（fully-specified vector pairs）均成立。我们利用计算得到的边界来筛选或剔除用于互连测试的向量对（vector pairs）。之后，我们构建了首个适用于此类互连结构的串扰故障模型（crosstalk fault model）。我们将向量对（vector pairs）划分为数据向量对（data vector pairs）与控制向量（control vectors）两类，明确了数据向量对需满足的覆盖保证条件，并制定了控制向量的设计要求：一是避免因短路造成电路损坏，二是尽可能降低不必要的良率损失（yield loss），三是缩减测试过程中所需使用的控制向量集合规模。我们同时提出了用于精简测试向量对的技术手段。最终，我们开发了一套包含任意互连结构表示方法的测试生成框架（test generation framework），并利用前述技术实现了向量对（vector pairs）的精简。实验结果表明，所提方法在保障安全测试与最优测试质量（test quality）的前提下，显著降低了测试成本（test cost）。