Data and code underlying the research of: Robust logic for STT based CIM

This work targets BNN-related applications. Given the inherent low sensing margins due to low TMR of STT devices, this work proposes an adaptive referencing mechanism to improve the sensing margin while performing logic operations in an STT-MRAM-based CIM. Reference signals are generated using multiple STT-MRAM devices and placed strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. The concept is demonstrated using an STT-MRAM model, which is calibrated using 1Mb characterized array at IMEC and is validated by deploying it in a BNN. This dataset includes schematic netlist files, raw data on the Excel sheets for latency and power estimations/simulation results, and Matlab codes for generating the graphs and figures in the associated publication.本研究聚焦于二值神经网络（Binary Neural Network, BNN）相关应用。鉴于自旋转移矩（Spin-Transfer Torque, STT）器件因隧穿磁阻（Tunneling Magnetoresistance, TMR）较低而固有的传感裕度不足问题，本研究提出一种自适应参考机制，可在基于自旋转移矩磁阻随机存取存储器（Spin-Transfer Torque Magnetoresistive Random-Access Memory, STT-MRAM）的存内计算（Compute-In-Memory, CIM）架构中执行逻辑运算的同时，提升传感裕度。该机制利用多颗STT-MRAM器件生成参考信号，并将其合理布设至存储阵列中，从而有效应对工艺偏差并精准补偿走线寄生效应。本研究采用经IMEC的1Mb表征阵列校准的STT-MRAM模型验证了该概念，并通过将其部署于二值神经网络中完成最终验证。本数据集包含原理图网表文件、用于延迟与功耗评估/仿真结果的Excel原始工作表数据，以及用于生成相关发表论文中各类图表的MATLAB代码。