TSMC 22nm工艺自适应时钟设计与测试数据
收藏资源简介：
本数据集是基于 TSMC 22nm 先进工艺节点构建的自适应时钟设计数据集，旨在为自适应时钟设计实现研究提供经过流片级工艺验证的标准参考资源。本数据集的数据结构依据工业界标准的后端设计流程进行组织，主要包含五类关键设计视图与验证数据：一是用于查看门级网表与仿真代码的Verilog文件，二是用于版图与原理图一致性检查及电路级仿真的 CDL 网表文件（SP格式）；三是描述物理边界与金属层信息的 LEF 设计规则文件；四是最终制造所需的 GDSII 版图文件；五是基于后仿GDSII版图进行的仿真测试波形文件FSDB，记录了功能的正确性。本数据集的使用面向快速频率调节与低功耗芯片设计领域，支持用户在 Linux 环境下配合主流 EDA 工具链进行调用。通过使用本数据集，研究人员可系统评估快速自适应时钟技术在先进工艺下的时序收敛性、功耗表现及面积效率，并为相关科研项目提供了高可靠性的 IP 核资源。该数据集已作为重点研发计划项目成果的重要组成部分，进行规范化汇交与管理。
This dataset is an adaptive clock design dataset constructed based on TSMC 22nm advanced process nodes, aiming to provide tapeout-level process-validated standard reference resources for research on adaptive clock design implementation. Its data structure is organized according to industry-standard backend design flows, and mainly includes five key design views and verification data: 1) Verilog files for viewing gate-level netlists and simulation codes; 2) CDL netlist files (SP format) for layout-versus-schematic checks and circuit-level simulation; 3) LEF design rule files describing physical boundaries and metal layer information; 4) GDSII layout files required for final manufacturing; 5) FSDB simulation test waveform files based on post-layout GDSII layouts, which record functional correctness. This dataset targets the fields of fast frequency regulation and low-power chip design, and supports users to invoke it with mainstream EDA toolchains in a Linux environment. By utilizing this dataset, researchers can systematically evaluate the timing convergence, power performance and area efficiency of fast adaptive clock technology under advanced process nodes, and provide highly reliable IP core resources for relevant scientific research projects. This dataset has been standardizedly submitted and managed as an important component of the achievements of key research and development program projects.
