低功耗可重构QC_LDPC电路/算法以及Serds电路仿真数据

低功耗可重构QC-LDPC电路及算法仿真数据测试主要内容是：针对设计适用于100G光传输系统的LDPC码进行软件仿真研究其性能,并设计可重构编译码器。为验证可重构QC-LDPC译码器电路性能，测试了不同的矩阵对应的误比特率和误码率、吞吐率及译码器的面积功耗等数据。为了综合测试提出的可重构QC-LDPC编解码器的计算效率和性能，针对不同的工作电压和频率，分别测试了基于ASIC和基于FPGA平台，在典型工作电压和工作频率情况下的计算效率。Serdes电路仿真数据主要针对28 Gb/s NRZ信号和40 Gb/s PAM4信号的SerDes物理层芯片的版图提取参数，开展相关指标性能仿真数据，包括输出数据波形、数据眼图和功耗数据项。The main content of the low-power reconfigurable QC-LDPC circuit and algorithm simulation data test is: We performed software simulations to investigate the performance of LDPC codes tailored for 100G optical transmission systems, and designed a reconfigurable encoder-decoder pair. To validate the performance of the proposed reconfigurable QC-LDPC decoder circuit, we tested datasets including bit error rate (BER), error rate, throughput, as well as the decoder's area and power consumption corresponding to different parity-check matrices. To comprehensively evaluate the computational efficiency and performance of the proposed reconfigurable QC-LDPC encoder-decoder pair, we tested their computational efficiency on both ASIC and FPGA platforms under various operating voltages and frequencies, as well as under typical operating voltage and frequency conditions. The SerDes circuit simulation data focuses on SerDes physical layer chips for 28 Gb/s NRZ signals and 40 Gb/s PAM4 signals. Using layout-extracted parameters of these chips, we conducted performance simulations for relevant indicators, including output data waveforms, data eye diagrams and power consumption data items.

搜集汇总

背景与挑战

背景概述

该数据集包含低功耗可重构QC-LDPC电路及算法的仿真数据，针对100G光传输系统，涉及LDPC码性能软件仿真、可重构编译码器设计，以及误比特率、误码率、吞吐率、面积功耗等测试，并在不同电压和频率下测试了ASIC和FPGA平台的计算效率。同时，还包括针对28 Gb/s NRZ和40 Gb/s PAM4信号的SerDes物理层芯片的版图提取参数仿真数据，涵盖输出数据波形、数据眼图和功耗指标。