This dataset supports the article entitled “Graceful Performance Modulation for Power-Neutral Transient Computing Systems” accepted for publication in IEEE Transactions on Computer-Aided Design of Int

Mendeley Data2024-01-31 更新140

OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis

集成电路设计

机器学习

Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design. It transforms a high-level description of hardware in a programming lan

NIAID Data Ecosystem90

针对传感器专用集成电路标准化设计规则采集实验数据

集成电路设计

传感器制造

本数据集包含工艺流程，关键工艺开发，流片报告，设计规则，器件模型，PDK及相应1项发明专利。数据来源于芯联集成电路制造股份有限公司开发的传感器专用集成电路制造平台上。类型是文件，共8件。其中文件1~2为设计规则，文件采集地点为浙江省绍兴市，采集时间2022年1月至2024年11月。文件3~6为传感器专用集成电路标准化设计工艺支撑数据，文件采集地点为浙江省绍兴市，采集时间2022年1月至2024年1

国家基础学科公共科学数据中心190

Data and code underlying the research of: SRIF-ADC for CIM accelerators

集成电路设计

神经形态计算

This targets neuromorphic and general-purpose arithmetic applications. A scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures is presented, suitable for stringe

Mendeley Data2024-06-25 更新130

Transistor dimensions used in this proposed topology.

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