Effects of 60Co gamma irradiation on three-dimensional Interconnection Structures Based on Through– Silicon via

With the development of Moores’ law, through-silicon via (TSV) has emerged as a critical technology for the realization of three-dimensional(3-D) packaged integrated circuits. However, with the widespread application of 3-D integrated microsystem technology in spacecraft, there is little work available on the radiation reliability of TSV. In this paper, the total ionizing dose (TID) effect of customized TSV test chips are studied by using the irradiation of 60Co gamma. The experimental results show that signal reflection coefficient (S11) increases and signal transmission coefficient (S21) decreases with the increase of cumulative dose. Furthermore, the metal-oxide-semiconductor (MOS) capacitance of interdigital electrode TSV structure decreases after gamma-ray irradiation. We propose that gamma-ray irradiation induced trap charges in the oxide layer causes the decrease of parasitic capacitance within TSV structure, resulting in the variation of characteristic impedance of TSV signal channel. Based on the resistance-inductance-conductance-capacitance (RLGC) equivalent circuit model, the TID characteristics of parasitic capacitance within TSV structure is verified using Advanced Design system (ADS) simulation software.